The fact, that data information must be combined with control information before transmission is a common aspect relating generally to telecommunication systems. In particular, this problem becomes severe, when a great plurality of user channels needs to be processed as it is the case in a CDMA system. A base transceiver station BTS of a CDMA system, to which the invention is applicable, is generally shown in FIG. 1.
Briefly summarized, the block diagram in FIG. 1 shows a base transceiver station BTS of a CDMA-system comprising a baseband transmitter TX, a baseband receiver RX and a HF section. In the transmitter TX, user data, for example in the form of ATM packets, is input into a channel encoder unit ENC via an ATM switch and a corresponding interface ATM IFX/IFC. The coded (and also interleaved) data is then modulated and spreaded by a baseband transmitter unit BBTX. The modulated data is then filtered and converted to an analog signal in the unit TRX-DIG, upconverted to the desired carrier frequency in the unit TRX-RF, amplified by a power amplifier unit MCPA and finally transmitted to an antenna ANT via a duplex filter.
In the receiving part of the HF section, two antennas (diversity reception) are commonly used in each sector to receive the signal which is then amplified in the unit LNA, downconverted in the unit TRX-RF, A/D converted and filtered in the unit TRX-DIG. Then the data is demodulated by a RAKE receiver/despreader in the receiver unit BBRX while random access channels (branched off by an intermediate filter unit BBIF) are detected and demodulated in the unit BBRA. The user data US are then decoded in the decoder unit DEC and transmitted to the ATM switch via an ATM interface ATM IFX/IFC.
In the CDMA base transceiver station BTS a bit-interleaving and de-interleaving is respectively performed in the encoder ENC in the baseband transmitter TX and the decoder DEC in the baseband receiver RX.
FIG. 2 shows a functional overview of the encoder ENC, where a plurality of data of individual user channels US1, US2, US3 are input as sequential packets including respective data bit sequences at {circle around (2)} into the ATM interface field programmable gate array FPGA ATM-IN. Upon channel coding in the FPGA CCOD-TCH interleaving is performed in the FPGA INTER-MOD at {circle around (3)}. That is, in FIG. 2 a number NUSCH of user channels (e.g. up to 300 different channels) input user data US at {circle around (2)} while control information CI for controlling the transmission of said data bit sequences is input at the digital signal processor DSP {circle around (1)} or generally by the FPGA INTER-MOD {circle around (3)}. The data bits plus their associated control information are interleaved and time-aligned in the FPGA modulator FPGA INTERMOD {circle around (3)} using a memory arrangement of 3 RAMs shown at {circle around (4)} and the interface FPGA RAM-IF1. The interleaved and time-aligned data is then transmitted to the baseband transmitter unit BBTX via the FPGA BBTX-OUT {circle around (5)}.
Thus, in addition to channel encoding and interleaving the encoder ENC in FIG. 2 combines data symbols from the user channels US1, US2, US3 . . . and control information CI, whereafter the combined information is provided to the baseband transmitter unit BBTX.
Data bits are provided in the form of code symbols representing one element of an alphabet of a digital modulation scheme such as QPSK or 16QAM. The control information associated with every code symbol is used to control other processing parts within the baseband transmitter unit BBTX. In general the BBTX unit spreads each code symbol to the common chip rate and performs a multiplication with the CDMA code and a weighting with a specific transmission power.
Furthermore, in such a transmitter, the data information of the user channel may be transmitted in individual frames. When several user channels are present, as is the case normally for example in a mobile radio communication system, then several user channels each provide digital data information which is to be inserted into the specific frames on the radio link between the transmitter of the base stations and the mobile stations. Each data frame may comprise data packets of several user channels which may arrive sequentially. Each packet is separately encoded and interleaved, before code symbols are formed and provided in parallel for all user channels to the CDMA modulator in the unit BBTX. The parallel processing towards the CDMA modulator is necessary because of the CDMA technique where all channels are added up prior to transmission.
Each packet thus contains a data bit sequence of a predetermined number of data bits (e.g. Mi bits) belonging to one user channel. The individual code symbols formed from the input data bit sequence in each packet may consist of e.g.
N=2 data bits representing the 4 possible states of a QPSK modulation (i.e. an I bit and a Q bit) and the control information CI may consist of e.g. L=4 control bits indicating specific control functions with respect to the corresponding code symbols.
As described above, in FIG. 2 a plurality of data of individual user channels US1, US2, US3, . . . are input as sequential packets comprising respective data bit sequences at {circle around (2)}. An interleaving is then performed in the FPGA INTER-MOD {circle around (3)} and the memory arrangement {circle around (4)}. In addition, control information CI is input to the DSP {circle around (1)}. Alternatively, the DSP {circle around (1)} or even the FPGA {circle around (3)} themselves may generate the control information CI. The control information is combined with the data bits, interleaved and time-aligned also in the FPGA {circle around (3)} together with the memory arrangement of the 3 RAMs shown at {circle around (4)}. The data bits in form of code symbols (representing one state of a digital modulation scheme) together with the associated control information is then transmitted to the baseband transmitter unit BBTX via the FPGA BBTX-OUT {circle around (5)}.
Although FIGS. 1, 2 show a special structure of a CDMA transmitter, generally, a digital transmitter using a frame-wise processing of data packets can be summarized as shown in FIG. 3. That is, a data source DS, provides digital data US in form of packets to a channel encoder CC. The channel encoder CC may be a convolutional encoder, however, also other codes may be used, e.g. block codes, turbo codes, etc. If the coder is a convolutional encoder it makes use of a specific rate and constraint length as predefined by the encoder polynomial. For example, the channel encoder ENC in FIGS. 1, 2 uses a convolutional coder with a rate r=1/2 and a constraint length c=9.
The channel encoded digital data output by the channel encoder CC are again data packets comprising a data bit sequence BS containing Mi data bits.
From the individual data bits of the data bit sequence code symbols each consisting of a number N of data bits are formed depending on the used digital modulation scheme. A write/read means W/R contains a selection means SM for extracting or selecting from the input data bit sequence BS data bits, which respectively belong to each other for forming such code symbols.
In a combining means COM the code symbols are combined with their corresponding control information CI (see for example FIG. 4). Then, the control information and the code symbols are provided as data bit sequence to an interleaver comprising an interleaving memory IM for performing the interleaving. Interleaving is an essential processing step in a mobile communication system to compensate errors introduced by flat fading more easily.
The write/read means W/R comprises a write means WM which writes the code symbols combined with the control information into the memory locations of the interleaving memory and a read means RM which reads out the stored information according to the interleaving scheme. The interleaved digital data sequence BS′ consisting of a specific number of code symbols Mi/N is output to the digital modulator MOD in the baseband transmitter unit BBTX which performs a modulation of the interleaved code symbols. For example, if the modulator uses a QPSK modulation, the bits are provided to the modulator as code symbols containing two bits, namely an I-bit and a Q-bit. The CDMA transmitter TX shown in FIG. 1 uses a QPSK modulation in the modulator BBTX. However, other digital modulation schemes can be used that require the provision of code symbols consisting of a different number of data bits. For example, a 16QAM method requires code symbols of four bits each and a 4QAM method requires code symbols of two bits each.
As is also seen in FIG. 3, the control information is read out together with the code symbols by the read means RM from the interleaving memory IM and is provided for example to the modulator MOD. For example, the control bits of the control information may indicate a frame start FS, a time slot start SS, a marker MA and/or a power bit PW for the respective code symbol. In particular, the power bit PW is an important control information used by the modulator MOD. Although FIG. 3 shows the provision of the control information to the modulator MOD only, this information can of course also be used in other units of the transmitter.
As described with respect to FIG. 3, the encoder ENC of the baseband transmitter TX comprises the channel coder CC, the combining means COM and a processing means formed by the interleaving memory IM and the write/read means W/R. However, having combined the control information and the code symbols in the combining means COM, a processing means may also take different forms depending on the specific processing desired in the transmitter for a specific modulation technique. However, conventionally the control information, i.e., the control bits, and the code symbols are processed separately in the processing means.
The invention should not be limited to the specific CDMA system or the transmitter shown in FIGS. 1, 2, 3, but any other processing scheme is applicable to the invention, as long as there is a need for processing the control information and code symbols, respectively data bits together.
Storage Problem of the Control Information and Code Symbols
In the course of the processing of the code symbols and the control bits in the processing means, there will always be the necessity to perform at least an intermediate storage of the information in a memory of the processing means, e.g. due to an interleaving process. Such a storage requirement may for example be satisfied by the interleaving memory IM.
Whilst the problem of how to store the data information together with the control information before transmission is thus a general problem that already occurs when considering only one user channel, of course, the problem becomes extremely severe when processing a great plurality of user channels (e.g. up to 300) as in FIGS. 1, 2, 3. The amount of data to be processed within each time interval of a frame (e.g. T=10 ms) gets very large. Therefore, the processing time and/or the memory requirements to perform channel encoding, bit-interleaving and time-alignment are very demanding.
FIG. 4 shows the conventional storage of data bits together with control bits in a memory, e.g. in the RAM memory shown in FIG. 2 or in the interleaving memory IM in FIG. 3. Such a combined storage is achieved by the conventional combining means COM as is shown in FIG. 3. The data bits and the associated control bits are listed in the rows, where each row is identified by an address. If data of a great plurality of user channels must be stored, preferably code symbols are formed before storing data to the RAM and the control bits are combined with such code symbols. This is possible as long as the control information is related to the code symbols finally transmitted over the air interface. Therefore, a set of two data bits in one row represents one code symbol of the data bit sequence which is to be transmitted.
As is shown in the example in FIG. 4, each data symbol (comprising two data bits) is used together with four control bits containing the control information and, if the memory positions only have a predetermined width of 4 bits, the complete information of 6 bits cannot be stored therein and thus the control information and the data symbols have to be stored in different memory locations (or different memories).
In addition, if the data symbols and a great variety of control information of many user channels has to be stored, a large memory, i.e., a large address space and many bits per address are necessary. Since it may be desired to store data symbols together with the control information for as many user channels as possible to keep RAM sizes and number of RAMs small, the memory should be configured such that as many memory positions as possible are available. For example, a 64 Kbit memory can be configured so as to have an address space of 16 kbit with a 4 bit width, while the same memory only has an address space of about 8 kbit with a bit width of 8. Thus, if data symbols of a specific length are to be stored together with a great variety of control information, obviously a large memory or more memories must be used or only a small number of user channels can be processed in a memory of a predetermined size.
FIG. 5 shows how conventionally each bit d0, d1 . . . of a code symbol etc. is stored at a separate memory location IM00, IM01 of an interleaving memory IM (or generally in a memory of a processing means). Already the separate storing of each individual bit of the data symbol thus requires a large memory. However, of course the situation becomes more severe, if also the control bits need to be stored in the interleaving memory together with the data bits. Furthermore, the large memory naturally increases the read/write access time to this memory as will be explained below. Moreover, if the control information (bits) belong to respective code symbols to be transmitted and each input data bit is stored separately, then the control information would have to be stored N-times (e.g. N=2 for QPSK).
Typical interleaving of an input data bit sequence BS comprising M data bits d0, d1 . . . dM−1 is shown in FIG. 5. FIG. 5 shows an interleaving matrix IM (i.e. in an interleaving memory) which is written row by row and read column by column for performing the interleaving of the data bits. Assuming that the input data bit sequence BS consists of M data bits and each bit is stored in its own memory location, then the interleaving matrix IM must have at least M memory locations IM00, IM01 etc. in an interleaver memory IM. The number of columns NW and the number of rows NR depends in fact on the interleaving depth which is here expressed as the number of columns before the writing of data bits jumps to the next row. The interleaving depth is always predetermined in an interleaver and if the interleaver depth is NW, then the storage of M data bits requires NR=┌M/NW┐ rows.
Conventionally, as is shown in FIG. 5, each data bit di of the input data bit sequence BS is stored at one memory location IMnw,nr defined by the respective row and column addresses nW=0, 1, 2 . . . NW−1 and nr=0 . . . , NR−1. As explained above, the interleaving process itself consists of a write and read process to and from the interleaving matrix in FIG. 5. Each of the processes (writing or reading) for all channels must be accomplished within a frame period when processing is performed in a frame-wise manner, but both processes have to be fast enough to be able to handle the great number of data packets of all users in the system within one frame period, even if the number of user channels US is very large.
For example, in FIG. 5, all data bits of one packet are written row by row starting in row 0 and all output bits are read column by column starting in column 0. Assuming the dimension of the bit-interleaving matrices to be M=NR*NW(number of rows*number of columns) the interleaving matrices must be filled completely by the data bit sequences contained in one frame in the predetermined time period of one frame. Afterwards the procedure is repeated in the next frame starting at rows 0 again. Therefore, in the afore-mentioned time interval of 10 ms each matrix has to be accessed (written or read) NR*NW times. And as packets arrive sequentially this writing or reading is also done sequentially.
In the conventional method during reading, the read means RM outputs the data bits as code symbols as required by the digital modulation method to the modulator MOD. For example, the read means RM may combine the bits d0 and dNW after two read cycles by accessing the respective two separate memory locations thereof and then provide the bits as code symbol to the modulator MOD.
It will be appreciated that a considerable amount of time is used to read and write the data if the number of user channels is large since all interleaver matrices are accessed sequentially. The time for accessing the matrices as well as the storage requirements for storing the matrices can therefore be very large when a great plurality of user channels is used or when the input data packets comprise a large number M of data bits. If, e.g., each data packet has M bits and U packets arrive in one frame, the total number of bits is either U*M bits (when each packet has the same length) or
      ∑          u      =      1        U    ⁢          ⁢      M    u  bits (when the packets have different lengths) for u=1 . . . U.
Whilst FIG. 5 for illustration purposes only shows the storage of the data bits d, of course the situation becomes more severe concerning the storage requirements, if the input data bit sequence containing M data bits is extended to also comprise a plurality of control bits for each data bit respectively code symbol as shown in FIG. 4.